Shift register (Old block)
This block realizes a shift register. At every input event, the
register is shifted one step.
- Register initial condition
A column vector. It contains the initial state of the register.
Properties : Type 'vec' of size -1
- always active: no
- direct-feedthrough: no
- zero-crossing: no
- mode: no
- regular inputs:
- port 1 : size [1,1] / type 1
- regular outputs:
- port 1 : size [1,1] / type 1
- number/sizes of activation inputs: 1
- number/sizes of activation outputs: 0
- continuous-time state: no
- discrete-time state: yes
- object discrete-time state: no
- name of computational function: delay
- SCI/macros/scicos_blocks/Linear/REGISTER_f.sci [view code]
Ramine Nikoukhah INRIA